Vhdl Parallel To Serial Converter

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Code VHDL - expandPFA:serial-to-parallel converterlibrary IEEE; use IEEE. All; use IEEE.STDLOGICunsigned.

All; use IEEE. Forget everything you know about C when writing HDL. Think of how the circuit needs to be hooked up. If you want a shift register you think of the equivalent schematic design. You were trying to use the for loop to create a 'timeline' for how long you shift. That can't be represented in hardware as a loop.

To measure time you need to have a counter and look at the value of the counter to determine when you're done.I'm not even sure you understand the problem statement you were given as an assignment. Do you want seven 8-bit serial-to-parallel converters? Is it okay for the parallel output to change while shifting or should it keep the last valid parallel output until you shift in the next parallel output?

Right now you have only a single Din that connects to only a single SIPO shift register. Later code connects the S output bus to all of the parallel outputs. Basically there is only a single instance of the shift register hooked up to all the outputs.Create a single instance of a SIPO register then instantiate that 7 times using a for loop (if you have to use a for loop per the assignment's requirements).IMO they should go back and teach schematic based circuit design in school, then teach HDLs by direct translation of schematics to HDL.

Code: library IEEE;use IEEE.STDLOGIC1164.all;use IEEE.STDLOGICunsigned.all;use IEEE.STDLOGICarith.all;entity serial isport(S1: in STDLOGICVECTOR( 0 downto 0);clk: in STDLOGIC;x: in STDLOGICVECTOR(0 downto 0);P1: out STDLOGICVECTOR(7 downto 0));end serial;architecture serial of serial iscomponent Dff isport(clk: in STDLOGIC;Din: in STDLOGIC;Q: out STDLOGIC);end component;signal s: stdlogicvector (7 downto 0);signal i: integer:=1;signal clk1: stdlogic;beginclk1 clk1,Din = S1(0),Q = s(0));M1:for i in 1 to 7 generateAi: Dffport map (clk = clk1,Din = s(i-1),Q = s(i));P1. Code: library IEEE;use IEEE.STDLOGIC1164.all;entity debounce isport(input: in STDLOGIC;cclk: in STDLOGIC;clr: in STDLOGICVECTOR (0 downto 0);output: out STDLOGIC);end debounce;architecture debounce of debounce issignal d1, d2, d3: STDLOGIC;beginprocess (cclk, clr(0))beginif clr(0) = '1' thend1 output,clk = clk381,x(0) = sw(1),P1 = led);Label2: clkdivport map(mclk = clk,clr(0) = sw(0),clk381 = clk381);Label3: debounceport map(input = JB(0),cclk = clk381,clr(0) = sw(0),output = output);end serialtop. The code you have posted doesnt show us anything.Your serial entity instantiates some other entity called 'DFF' that you didnt show the code for.and I dont know what this debounce entity is for. It doesnt actually debounce the values, it appears to only detect the bounces, and you have set the output to detect opposite values on D2/D1 and D3.It's pretty obvious that the DFF is a D type Flip-Flop, now whether or not it's coded correctly is anyone's guess.The debounce is a misnamed edge detector and synchronizer (well as currently written).The code also uses the non-standard libraries stdlogicunsigned and stdlogicarith (taught by those schools that use antiquated syntax). Cclk'event and cclk = '1' is being used instead of risingedge(cclk). The code (targeted for an FPGA) has a gated clock! The OP is generating clocks from a counter (in an FPGA) instead of generating clock enables.

This is another good example of combining all the bad coding practices into a single design. I understand gated clock is a bad design practice but this was done in order to 'freeze' the parallel.I thought that maybe the arduino is not synchronised which arose the encountered problem.if I remove the debounce codes and the gated clock still I get no results.Of course you don't get results, because you are using the 'I'll just randomly try this and see if it works' debug methodology.First carefully check the simulation and the TEST VECTORS you are using. Garbage In = Garbage Out (GIGO). If you are absolutely sure you've supplied the correct vectors to your design in the simulation testbench, now you should make sure the design is doing exactly what you want.In the case of using counter generated clocks I would strongly recommend adding delays to all the counter outputs to emulate the actual hardware and to prevent the simulator from lying to you if there is some delta time race condition (I've seen this happen before, but that was a long time ago when RTL simulation was in it's infancy).

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But adding the delays will ensure that nothing funny is going on with those 'clocks' (a.k.a. Counter outputs).I also strongly advise you rethink how you design stuff this was done in order to 'freeze' the parallel, this would never get past a design review with me working at the same company. If you want to freeze the input use a synchronized clock enable.